The WaferSight 2+ bare wafer geometry measurement system enables wafer manufacturers to meet the demanding lithography and CMP requirements imposed by leading-edge IC fabs. Issues with wafer flatness can cause defocus defects during patterning. Local topography defects can cause defocus or overlay issues. Nanotopography also influences the uniformity of material removal during CMP. Deviations in a wafer’s Edge Roll Off (ERO) can cause meniscus breakdown during immersion lithography; create defocus defects near the wafer edge; and interfere with the ability to print yielding edge die.
In a single pass, the WaferSight 2+ wafer geometry metrology system measures wafer geometry over many spatial wavelengths, from nanotopography to wafer bow, to address these issues. WaferSight 2+ provides the precision and tool-to-tool matching required for volume production of polished silicon, epitaxial silicon and engineered substrates, for advanced nodes. Concurrent measurement of both front and back surfaces on WaferSight 2+ allows wafer manufacturers to perform comprehensive metrology on each wafer to ensure that they are shipping first quality substrates to their IC customers.
- WaferSight 2+ offers simultaneous flatness, high-resolution edge roll-off and dual-sided nanotopography measurements to meet IC fabs’ requirements for sub-28nm device manufacturing, while increasing bare wafer geometry measurement productivity by up to 40% over that of WaferSight 2
- High quality optics and chuckless architecture support artifact-free nanotopography measurement
- Detection of localized topography defects on front and back surfaces of polished, epitaxial and SOI wafers, as well as high resolution ERO with 1mm edge exclusion, are provided with the Advanced Metrics Package (AMP)
- The ability to match WaferSight 2+ to existing WaferSight 2 tools provides flexibility for work-in-progress routing and preserves the manufacturing baseline
- WaferSight 2+ is designed to be upgradable to meet metrology requirements for the 1Xnm design nodes
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